Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based o...

• Autor(es): Goes, J. ; Esperança, B. ; Tavares, R. ; Galhardo, A. ; Paulino, N. ; Silva, M. Madeiros
• Data: 2008
• Identificador Persistente: http://hdl.handle.net/10362/4062
• Origem: Repositório Institucional da UNL
• Tipo de Documento: Research paper
• Idioma: Inglês

Descrição

IEEE International Symposium on Circuits and Systems, pp. 220 – 223, Seattle, EUA This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with a power-and-area efficiency better than 0.5 pJmm2 per conversion. This competes with the most efficient architectures available today namely, ΣΔ and self-calibrated pipeline. The 2 stages of the ADC are based on a new 1.5-bit mismatch-insensitive MDAC and simulations demonstrate that a THD of –79 dB and an ENOB better than 12 bits can be reached without self-calibration.