Encontrados 13 documentos, a visualizar página 1 de 2
A multiplying-by-two CMOS amplifier for high-speed ADCs based on parametric amp...
Goes, J.; Oliveira, J. P.; Paulino, N.; Fernandes, J.; Paisana, J.15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poznan, Polónia ; In this paper a new structure for a multiplying-by-two amplifier is proposed. It is implemented by switching MOS capacitors with floating sources from inversion into depletion dropping the capacitance values in the amplification phase. Low-power is achieved since no operational amplifiers are requ...
New simple digital self-calibration technique for pipeline ADCs using the inter...
Goes, J.; Paulino, N.; Evans, G.; Figueiredo, M.IEEE International Symposium on Circuits and Systems, pp. 232 – 235, Seattle, EUA ; This paper describes a new digital-domain selfcalibration technique for high-speed pipeline A/D converters using the internal thermal noise as input stimulus. This lowamplitude noise is amplified and recycled by the ADC itself and, due to the successive foldings, it is naturally converted into uniform noise. This noise is then ...
Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based o...
Goes, J.; Esperança, B.; Tavares, R.; Galhardo, A.; Paulino, N.; Silva, M. MadeirosIEEE International Symposium on Circuits and Systems, pp. 220 – 223, Seattle, EUA ; This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with a power-and-area efficiency better than 0.5 pJmm2 per conversion. This competes with the most efficient architectures available today namely, ΣΔ and self-calibrated pipeline. The 2 stages of the ADC are based on a new 1.5-bit mismatch-insensitive MDAC and...
Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification us...
Goes, J.; Paulino, N.; Galhardo, A.IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUA ; A low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs openloop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive fron...
A CMOS variable width short-pulse generator circuit for UWB RADAR applications
Goes, J.; Paulino, N.; Steiger-Garção, A.IEEE International Symposium on Circuits and Systems, pp. 2713 – 2716, Seattle, EUA ; This paper describes a variable width short pulse generator circuit for UWB radar applications, designed in a 0.18μm CMOS technology. This circuit is capable of generating pulses with a duration from 0.7 ns to 3.5 ns and an amplitude of 0.7 V with a 50 Ω load. The power supply voltage can be as low as 1.5 V and uses only 2.3 ...
Optimization of multi-stage amplifiers in deep-submicron CMOS using a distribut...
Goes, J.; Santos-Tavares, R.; Paulino, N.; Higino, J.; Oliveira, J. P.IEEE International Symposium on Circuits and Systems, pp. 724 – 727, Seattle, EUA ; This paper presents a framework for time-domain optimization of amplifiers employing a parallel genetic algorithm based on a message passing interface. This methodology achieves a considerable reduction in the optimization time (up to 19 times faster than a serial implementation). Increasing the processing capacity allows searc...
New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification
Goes, J.; Oliveira, J. P.; Paulino, N.; Fernandes, J.; Paisana, J.15th IEEE International Conference on Electronics, Circuits and Systems, Malta ; In this paper a new time-interleaved 1.5-bit MDAC circuit is proposed. This circuit is well suited to be used in ultra low-power high-speed 4-to-8 bits pipeline ADCs. The required gain of two is implemented by switching a MOS capacitor from inversion into depletion within a clock-cycle. Low-power is achieved since no operational a...
Multi-bit sigma-delta modulators with enhanced dynamic-range using non-linear D...
Goes, J.; Paulino, N.; Custódio, J. R.15th IEEE International Conference on Electronics, Circuits and Systems, Malta ; This paper presents the possibility of employing nonlinear low-resolution DACs in the feedback paths of multi-bit second-order Sigma-Delta modulators. The proposed technique is particularly attractive in applications such as hearing aids, requiring a very large dynamic range and medium signal-tonoise-plus-distortion-ratio. As demo...
Design and testing of a radiation hardened 13-bit 80 MS/s pipeline ADC implemen...
Goes, J.; Paulino, N.; Vaz, B.; Rodrigues, M.; Faria, P.; Monteiro, R.; Penetra, N.; Domingues, T.Second International Workshop on Analog and Mixed Signal Integrated Circuits for Space Applications (AMICSA 2008), Sintra, Portugal, Setembro de 2008
Low-voltage low-power CMOS analogue circuits for Gaussian and uniform noise gen...
Evans, G.; Goes, J.; Garção, A. Steiger; Ortigueira, M.D.; Paulino, N.; Lopes, J. SousaIEEE International Symposium on Circuits and Systems, MAY 25-28, 2003, Bangkok, Thailand. (ISI Web of Science) ; A CMOS analogue circuit for Gaussian noise generution as well as a novel circuitfor transforming Gaussian noise into uniform noise, hoth.designed/or operating with a supply voltoge o/ I . S K arepresented. Both circuits are optimizedfor U 0 . 3 5st~an - dord CMOS technology using an equation-based d...
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