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Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based o...
Goes, J.; Esperança, B.; Tavares, R.; Galhardo, A.; Paulino, N.; Silva, M. MadeirosIEEE International Symposium on Circuits and Systems, pp. 220 – 223, Seattle, EUA ; This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with a power-and-area efficiency better than 0.5 pJmm2 per conversion. This competes with the most efficient architectures available today namely, ΣΔ and self-calibrated pipeline. The 2 stages of the ADC are based on a new 1.5-bit mismatch-insensitive MDAC and...
Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification us...
Goes, J.; Paulino, N.; Galhardo, A.IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUA ; A low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs openloop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive fron...
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