Autor(es):
Goes, J. 
; Oliveira, J. P. ; Paulino, N. ; Fernandes, J. ; Paisana, J.
Data: 2008
Identificador Persistente: http://hdl.handle.net/10362/4057
Origem: Repositório Institucional da UNL
Detalhes do Documento
New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification
Descrição
15th IEEE International Conference on Electronics, Circuits and Systems, Malta In this paper a new time-interleaved 1.5-bit MDAC circuit is proposed. This circuit is well suited to be used in ultra low-power high-speed 4-to-8 bits pipeline ADCs. The required gain of two is implemented by switching a MOS capacitor from inversion into depletion within a clock-cycle. Low-power is achieved since no operational amplifiers are required but, instead, simple source-followers are used. Simulation results of a complete front-end stage of a 6-bit 2-channel pipeline ADC demonstrate the efficiency of the proposed technique.
15th IEEE International Conference on Electronics, Circuits and Systems, Malta In this paper a new time-interleaved 1.5-bit MDAC circuit is proposed. This circuit is well suited to be used in ultra low-power high-speed 4-to-8 bits pipeline ADCs. The required gain of two is implemented by switching a MOS capacitor from inversion into depletion within a clock-cycle. Low-power is achieved since no operational amplifiers are required but, instead, simple source-followers are used. Simulation results of a complete front-end stage of a 6-bit 2-channel pipeline ADC demonstrate the efficiency of the proposed technique.
Tipo de Documento
Documento de conferência
Idioma Inglês
Idioma Inglês
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