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A multiplying-by-two CMOS amplifier for high-speed ADCs based on parametric amp...
Goes, J.; Oliveira, J. P.; Paulino, N.; Fernandes, J.; Paisana, J.15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poznan, Polónia ; In this paper a new structure for a multiplying-by-two amplifier is proposed. It is implemented by switching MOS capacitors with floating sources from inversion into depletion dropping the capacitance values in the amplification phase. Low-power is achieved since no operational amplifiers are requ...
New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification
Goes, J.; Oliveira, J. P.; Paulino, N.; Fernandes, J.; Paisana, J.15th IEEE International Conference on Electronics, Circuits and Systems, Malta ; In this paper a new time-interleaved 1.5-bit MDAC circuit is proposed. This circuit is well suited to be used in ultra low-power high-speed 4-to-8 bits pipeline ADCs. The required gain of two is implemented by switching a MOS capacitor from inversion into depletion within a clock-cycle. Low-power is achieved since no operational a...
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