Wafer-level chip-scale packaging for low-end RF products

• Author(s): Bartek, M. ; Zilmer, G. ; Teomin, D. ; Polyakov, A. ; Sinaga, S. M. ; Mendes, P. M. ; Burghartz, J. N.
• Date: 2004
• Persistent ID: http://hdl.handle.net/1822/1647
• Origin: RepositóriUM - Universidade do Minho
• Subject(s): Wafer level packaging WLP; Chip scale packaging CSP; System-on-chip Soc; Embedded passives; Crosstalk suppression
• Document Type: Conference Object
• Language: English

Description

This paper gives a short overview of waferlevel chip-scale packaging technology and analyses its added value in the packaging of RF ICs. Particularly, the possibilities of substrate crosstalk suppression by substrate thinning and trenching together with embedding of rf passives (inductors, antennas) are addressed. The Shellcasetype wafer-level packaging solution is used as a study case presenting its fabrication aspects and its potential for RF IC packaging.