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Integrated chip-size antennas for wireless microsystems : fabrication and desig...
Mendes, P. M.; Polyakov, A.; Bartek, M.; Burghartz, J. N.; Correia, J. H.This paper reports on fabrication and design considerations of an integrated folded shorted-patch chip-size antenna for applications in short-range wireless microsystems and operating inside the 5–6 GHz ISM band. Antenna fabrication is based on wafer-level chip-scale packaging (WLCSP) techniques and consists of two adhesively bonded glass wafers with patterned metallization and through-wafer electrical intercon...
High-resistivity polycrystalline silicon as RF substrate in wafer-level packaging
Polyakov, A.; Sinaga, S. M.; Mendes, P. M.; Correia, J. H.; Bartek, M.; Burghartz, J. N.High-resistivity polycrystalline silicon (HRPS) is presented as a novel low-cost and low-loss substrate for radio-frequency (RF) passive components in wafer-level packaging and integrated passive networks. A record quality factor (Q¼11; 1 GHz; 34 nH) and very low loss (0.65 dB=cm; 17 GHz) are demonstrated for inductors and coplanar waveguides, respectively, on HRPS.
Wafer-level packaging fo RF applications : using high resistivity polycrystalli...
Polyakov, A.; Sinaga, S. M.; Mendes, P. M.; Bartek, M.; Correia, J. H.; Burghartz, J. N.High-resistivity polycrystalline silicon (HRPS) wafers are explored as a novel low-cost and low-loss substrate in Wafer-Level Chip-Size Packaging (WLCSP) for RF applications. The WLCSP solution we demonstrate is based on adhesive bonding of a HRPS wafer to a silicon wafer with active devices. After bonding, the IC wafer is thinned below 50 µm and selectively removed to expose its front-side contact pads. The HR...
An integrated folded-patch antenna for wireless microsystems
Mendes, P. M.; Polyakov, A.; Bartek, M.; Burghartz, J. N.; Correia, J. H.A fully integrated, folded-patch antenna for operation at 5.62 GHz and application in wireless sensor networks has been realized and characterized. Overall dimensions of 4x4x1 mm3, measured bandwidth of 100 MHz and an efficiency of 32% were achieved. The antenna fabrication is based on wafer-level packaging techniques and consists of two adhesively bonded glass substrates with through substrate electrical vias ...
Characterization of high-resistivity polycrystalline silicon substrates for waf...
Bartek, M.; Polyakov, A.; Sinaga, S. M.; Mendes, P. M.; Correia, J. H.; Burghartz, J. N.High-resistivity polycrystalline silicon (HRPS) wafers are explored as a novel low-cost and low-loss substrate for radio-frequency (RF) passive components in wafer-level packaging (WLP) and integrated passive networks. A record quality factor (Q=11; 1 GHz; 34 nH) and very low loss (0.65 dB/cm; 17 GHz) are demonstrated for inductors and coplanar wave guides, respectively. The waferlevel packaging solution is bas...
An integrated folded-patch chip-size antenna using high-resistivity polycrystal...
Mendes, P. M.; Polyakov, A.; Bartek, M.; Burghartz, J. N.; Correia, J. H.High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate complex RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form facto...
Wafer-level integration of on-chip antennas and RF passives using high-resistiv...
Mendes, P. M.; Sinaga, S. M.; Polyakov, A.; Bartek, M.; Burghartz, J. N.; Correia, J. H.High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas and RF passive components (e.g. large inductors) in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate large RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while prov...
Wafer-level chip-scale packaging for low-end RF products
Bartek, M.; Zilmer, G.; Teomin, D.; Polyakov, A.; Sinaga, S. M.; Mendes, P. M.; Burghartz, J. N.This paper gives a short overview of waferlevel chip-scale packaging technology and analyses its added value in the packaging of RF ICs. Particularly, the possibilities of substrate crosstalk suppression by substrate thinning and trenching together with embedding of rf passives (inductors, antennas) are addressed. The Shellcasetype wafer-level packaging solution is used as a study case presenting its fabricatio...
Extraction of glass-wafers electrical properties based on S-parameters measurem...
Mendes, P. M.; Polyakov, A.; Bartek, M.; Burghartz, J. N.; Correia, J. H.The measured S-parameters of a coplanar waveguide (CPW) propagating the dominant mode were used to obtain the electrical permittivity and the dielectric loss tangent of three different glass wafers: non-alkaline Schott AF45, Corning Pyrex #7740 and Hoya SD-2. These properties were obtained up to 10 GHz. The obtained values were used together with the CPW model in ADS to obtain the simulated S-parameters for the...
Processability and electrical characteristics of glass substrates for RF wafer-...
Polyakov, A.; Mendes, P. M.; Sinaga, S. M.; Bartek, M.; Rejaei, B.; Correia, J. H.; Burghartz, J. N.Various types of glass substrates have been compared with respect to their suitability as a low-loss substrate in wafer-level chip-scale packaging for RF applications. Processability has been evaluated by fabrication of shallow and deep recesses using wet etching in HF (/H3PO4) solutions. Electrical characteristics (dielectric constant and attenuation) have been extracted from measurements on coplanar wave guid...
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