An integrated folded-patch chip-size antenna using high-resistivity polycrystal...

• Author(s): Mendes, P. M. ; Polyakov, A. ; Bartek, M. ; Burghartz, J. N. ; Correia, J. H.
• Date: 2004
• Persistent ID: http://hdl.handle.net/1822/1619
• Origin: RepositóriUM - Universidade do Minho
• Subject(s): Integrated antenna; Folded antenna; Small antenna; Wireless microsystem
• Document Type: Conference Object
• Language: English

Description

High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate complex RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. A folded-patch antenna with dimensions of 2.5x2.5x1 mm3, operating at 5.7 GHz was analysed considering a 10 kΩ-cm HRPS wafer. The antenna has a –10 dB return loss bandwidth of 50 MHz and an efficiency of 58 %, a performance comparable to glass substrates.