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High-resistivity polycrystalline silicon as RF substrate in wafer-level packaging
Polyakov, A.; Sinaga, S. M.; Mendes, P. M.; Correia, J. H.; Bartek, M.; Burghartz, J. N.High-resistivity polycrystalline silicon (HRPS) is presented as a novel low-cost and low-loss substrate for radio-frequency (RF) passive components in wafer-level packaging and integrated passive networks. A record quality factor (Q¼11; 1 GHz; 34 nH) and very low loss (0.65 dB=cm; 17 GHz) are demonstrated for inductors and coplanar waveguides, respectively, on HRPS.
Wafer-level packaging fo RF applications : using high resistivity polycrystalli...
Polyakov, A.; Sinaga, S. M.; Mendes, P. M.; Bartek, M.; Correia, J. H.; Burghartz, J. N.High-resistivity polycrystalline silicon (HRPS) wafers are explored as a novel low-cost and low-loss substrate in Wafer-Level Chip-Size Packaging (WLCSP) for RF applications. The WLCSP solution we demonstrate is based on adhesive bonding of a HRPS wafer to a silicon wafer with active devices. After bonding, the IC wafer is thinned below 50 µm and selectively removed to expose its front-side contact pads. The HR...
Characterization of high-resistivity polycrystalline silicon substrates for waf...
Bartek, M.; Polyakov, A.; Sinaga, S. M.; Mendes, P. M.; Correia, J. H.; Burghartz, J. N.High-resistivity polycrystalline silicon (HRPS) wafers are explored as a novel low-cost and low-loss substrate for radio-frequency (RF) passive components in wafer-level packaging (WLP) and integrated passive networks. A record quality factor (Q=11; 1 GHz; 34 nH) and very low loss (0.65 dB/cm; 17 GHz) are demonstrated for inductors and coplanar wave guides, respectively. The waferlevel packaging solution is bas...
Wafer-level integration of on-chip antennas and RF passives using high-resistiv...
Mendes, P. M.; Sinaga, S. M.; Polyakov, A.; Bartek, M.; Burghartz, J. N.; Correia, J. H.High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas and RF passive components (e.g. large inductors) in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate large RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while prov...
Wafer-level chip-scale packaging for low-end RF products
Bartek, M.; Zilmer, G.; Teomin, D.; Polyakov, A.; Sinaga, S. M.; Mendes, P. M.; Burghartz, J. N.This paper gives a short overview of waferlevel chip-scale packaging technology and analyses its added value in the packaging of RF ICs. Particularly, the possibilities of substrate crosstalk suppression by substrate thinning and trenching together with embedding of rf passives (inductors, antennas) are addressed. The Shellcasetype wafer-level packaging solution is used as a study case presenting its fabricatio...
Processability and electrical characteristics of glass substrates for RF wafer-...
Polyakov, A.; Mendes, P. M.; Sinaga, S. M.; Bartek, M.; Rejaei, B.; Correia, J. H.; Burghartz, J. N.Various types of glass substrates have been compared with respect to their suitability as a low-loss substrate in wafer-level chip-scale packaging for RF applications. Processability has been evaluated by fabrication of shallow and deep recesses using wet etching in HF (/H3PO4) solutions. Electrical characteristics (dielectric constant and attenuation) have been extracted from measurements on coplanar wave guid...
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