Different built-in self testing schemes for RF circuits have been developed resorting to peak voltage detectors. These are simple to implement but provide a conditional RF power measurement accuracy as impedance is assumed to be known. A true power detector is presented which allows obtaining more accurate measurements, namely as far as output load variations are concerned. The theoretical fundaments underlinin...
In this paper, we report the impact of the parasitic capacitances in the modeling and analysis of advanced floating gate (FG) non-volatile memory (NVM) devices, especially on the coupling ratio. Due to the poor accuracy of the existing capacitance model when compared to practice, an approach to include the parasitic capacitances has been established. Measurement results from two transistor (2T) Fowler-Nordheim ...
This special issue of the VLSI Design journal is dedicated to the 13th IEEE International Mixed Signals Testing Workshop (IMSTW) and 3rd IEEE International GHz/Gbps Test Workshop (GTW), held in June 2007 at Póvoa de Varzim, Portugal.
Abstract—Test stimuli generation and power consumption are two issues that jeopardize the design of built-in self test schemes. The LNA testing approach presented herein relies on converting the amplifier into an oscillator and on using a low-power correlator to obtain a signature from the cross-correlation between the dynamic power supply current and the LNA’s output voltage. In test mode a high fa...
A new technique is proposed to tackle in-circuit testing of embedded RF blocks. It relies on observing the cross-correlation between its output voltage and power supply current, using a translinear cross-correlator circuit. Although a structural test is performed, simulation results show that fault detection criteria can be established based on acceptable deviations of performance characterization parameters. T...
This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor, which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester. Building these test operations on-chip allows for simplifying exte...
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