Encontrados 7 documentos, a visualizar página 1 de 1
Computational Block Templates Using Functional Programming Models
Paulo Ferreira; João Canas Ferreira; José Carlos AlvesThe elaboration of computational blocks using declarative models, typical of functional languages, allows the use of a parameterized template for the hardware design. This paper shows how such a template can be created, for the hardware implementation of computational blocks based on a declarative model, and how it can be used to provide design space exploration alternatives and hardware acceleration for Erlang...
FPGA Implementation of Autonomous Navigation Algorithm with Dynamic Adaptation ...
José Sá; João Canas Ferreira; José Carlos AlvesThe main goal of this work is to build an hardware-aided autonomous navigation system based on real-time stereo images and to study Partial Reconfiguration aspects applied to the system. The system is built on an reconfigurable embedded development platform consisting of an IBM PowerPC 440 processor embedded in a Xilinx Virtex-5 FPGA to accelerate the most critical task. Three Reconfigurable Units were incorpor...
A Remote Demonstrator for Dynamic FPGA Reconfiguration
Hugo Marques; João Canas FerreiraThis paper presents a demonstrator for partial reconfiguration of FPGAs applied to image processing tasks. The main goal of the project is to develop an environment whichallows users to assess some of the advantages of using dynamic reconfiguration. The demonstration platform is built around a Xilinx Virtex-5 FPGA, which is used to implement a chain of four reconfigurable filters for processing images. Using a ...
Automatic Generation of Cellular Automata on FPGA
André Lima; João Canas FerreiraCellular automata (CA) have been used to study a great range of fields, through the means of simulation, owing to its computational power and inherent characteristics. Furthermore, CAs can perform task-specific processing. Spacial parallelism, locality and discrete nature are the main features that enable mapping of CA onto the regular architecture of an FPGA; such a hardware solution significantly accelerates ...
Flexible Use of IP Cores on Dynamically Reconfigurable Systems
Miguel L. Silva; João Canas Ferreira; José Silva MatosThe advantages of dynamic reconfiguration can only be exploited if devices, tools and design flows are available to support the partial reconfiguration of FPGA-based systems. For a number of applications, enabling the swap of cores at run-time, under software control, is an essential feature that allows tailoring the system response to the needs of different methods, standards and power/performance requirements...
Exploiting dynamic reconfiguration of platform FPGAs: Implementation issues
Miguel Silva; João Canas FerreiraThe effective use of dynamic reconfiguration requires the designer to address many implementation issues. The market introduction of feature-full platform FPGAs equipped with embedded CPU blocks expands the number of situations where dynamic reconfiguration may be applied to improve overall performance and logic utilization. The paper compares the design of two similar systems supporting dynamic reconfiguration...
Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems
Miguel Silva; João Canas FerreiraThis paper describes a tool that creates partially-reconfigurable modules from the bitstreams of individual component modules. The resulting modules are intended for use in applications that exploit partial dynamic reconfiguration. The tool is integrated in a design flow particularly aimed at dynamically-reconfigurable platform FPGAs. The corresponding design flow is described together with a basic run-time sup...
| Financiadores do RCAAP | |||||||
|
|
|
|
|
|
||