This paper discusses the benefits of using a hardwarecoprocessor to improve the determinism and performanceof a Real-Time Kernel. The proposed coprocessor wasmodeled with the VHDL hardware description language andimplemented in a FPGA (Field-Programmable Gate Array).It is able to manage (schedule, preempt and dispatch) several tasks, either periodic or aperiodic. The preemption of the task running on the Centra...
The necessity for better radios with increased flexibility,easier design and verification led a paradigm shift infavour of the Software-Defined Radio (SDR). On the otherhand, the SDR implementation of Next Generation WirelessNetworks (NGWN) will require significantly higher power efficiency than current processors can provide.In this paper, we present a baseband processing architecturedesigned to shorten the ga...
This paper introduces the fundamentals of real-time operating systems. The topics covered include the motivation for using this class of systems, the application domains, the tasks used for their implementation and the scheduling policies normally employed.Keywords: Real-time systems, operating systems, task scheduling ; Este artigo faz uma introdução aos sistemas operativos de tempo real. ...
This paper discusses the implementation, features and use of the OReK kernel - an object-oriented, fully preemptive real-time kernel implemented in C++. The OReK kernel is pratically platform independent, containing only small and localized code segments that are platform dependent. Currently it can be used in PC's with an Intel x86 compatible processor family with MSDOS, because it needs to configure and acces...
This paper describes the ARPA project.The aim of this project is to develop an opensource System-on-Chip model for real-time applications.The main component of the SoC is a MIPS based RISC processor. It is implemented using a pipelined Simultaneous Multithreading (SMT) structure, which allows exploring the Instruction and Task Level Parallelism, decrease tlie contextswitching time and a...
The CLAN intellectual property core is a CAN 2.0b controller developed at the Electronics and Telecommunications Department of the University of Aveiro, for research and educational purposes and in particular with the aim of providing the adequate hardware support to implement and validate higher layer protocols such as TTCAN or FTT- CAN.It was modelled at RTL level using the VHDL hardware description language,...
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