Autor(es):
E. Martins 
; P. Neves ; J. Fonseca
Data: 2013
Origem: Electrónica e Telecomunicações
Assunto(s): PSCoP; scheduling coprocessor; PSCoP; scheduling coprocessor
Detalhes do Documento
PSCoP: A Planning Scheduler Coprocessor
Descrição
The use of a centralised planning scheduler in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational flexibility and timeliness guarantees.In this paper a preliminary implementation of a hardware scheduling coprocessor based in the planning paradigm is presented. The coprocessor is installed in a special node of the fieldbus, the bus arbiter, and generates scheduling tables to be dispatched by the node CPU. With this solution it is possible to decrease the response time to changes in the system configuration or message parameters of the softwarebased planning scheduler. This opens the possibility of allowing automatic on-line changes requested by system nodes in addition to the ones requested by human operators, thus improving system reactivity.In this paper the focus is on the coprocessor’s interface with the node CPU and its overall functionality. Initial calculations showing the feasibility of the unit and its expected performance are also derived. The use of a centralised planning scheduler in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational flexibility and timeliness guarantees.In this paper a preliminary implementation of a hardware scheduling coprocessor based in the planning paradigm is presented. The coprocessor is installed in a special node of the fieldbus, the bus arbiter, and generates scheduling tables to be dispatched by the node CPU. With this solution it is possible to decrease the response time to changes in the system configuration or message parameters of the softwarebased planning scheduler. This opens the possibility of allowing automatic on-line changes requested by system nodes in addition to the ones requested by human operators, thus improving system reactivity.In this paper the focus is on the coprocessor’s interface with the node CPU and its overall functionality. Initial calculations showing the feasibility of the unit and its expected performance are also derived.
The use of a centralised planning scheduler in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational flexibility and timeliness guarantees.In this paper a preliminary implementation of a hardware scheduling coprocessor based in the planning paradigm is presented. The coprocessor is installed in a special node of the fieldbus, the bus arbiter, and generates scheduling tables to be dispatched by the node CPU. With this solution it is possible to decrease the response time to changes in the system configuration or message parameters of the softwarebased planning scheduler. This opens the possibility of allowing automatic on-line changes requested by system nodes in addition to the ones requested by human operators, thus improving system reactivity.In this paper the focus is on the coprocessor’s interface with the node CPU and its overall functionality. Initial calculations showing the feasibility of the unit and its expected performance are also derived. The use of a centralised planning scheduler in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational flexibility and timeliness guarantees.In this paper a preliminary implementation of a hardware scheduling coprocessor based in the planning paradigm is presented. The coprocessor is installed in a special node of the fieldbus, the bus arbiter, and generates scheduling tables to be dispatched by the node CPU. With this solution it is possible to decrease the response time to changes in the system configuration or message parameters of the softwarebased planning scheduler. This opens the possibility of allowing automatic on-line changes requested by system nodes in addition to the ones requested by human operators, thus improving system reactivity.In this paper the focus is on the coprocessor’s interface with the node CPU and its overall functionality. Initial calculations showing the feasibility of the unit and its expected performance are also derived.
Tipo de Documento
Documento de conferência
Idioma Inglês
Editor(es) ;
Idioma Inglês
Editor(es) ;
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