Autor(es):
Alves, Gustavo R. 
; Ferreira, José M.
Data: 1999
Identificador Persistente: http://hdl.handle.net/10400.22/4320
Origem: Repositório Científico do Instituto Politécnico do Porto
Detalhes do Documento
A system verification strategy based on the BST infrastructure
Descrição
A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.
A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.
Tipo de Documento
Documento de conferência
Idioma Inglês
Idioma Inglês
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